Notes on I2C

I2C is a two wire bus protocol used for communication between chips.

Physical layer

The key in understanding the I2C protocol, is in understanding its simple but clever electrical design, as depicted in the figure below:

The bus consists of two wires, which are called Serial Clock (SCL) and Serial Data (SDA). Both of these wires are connected with pull-up resistors to the positive supply voltage. Now the trick is that each device on the bus can only actively pull a line to ground, producing a logical 0. A device can not actively make the line high, so there is no risk of electrical conflicts. The line only becomes high again (logical 1) when no device is asserting the line (i.e. pulling it to ground).

Whith this physical layer picture in mind, we can look at the next layer, the medium access layer.

Media access

The bus is idle when no device is asserting any of the lines, so both the SCL and SDA lines are high.

During normal data transfers, SDA is only allowed to change when SCL is low. When SCL is high, SDA must remain stable so the receiver can sample a valid bit value. Any transition on SDA while SCL is high is interpreted as a Start or Stop condition, not as data.

When the bus is idle, both SCL and SDA are high. A Start condition is signaled by SDA going low while SCL remains high. (Note that this way of signalling a Start condition is the only viable option. Changing SCL first could be mistaken for a regular clock pulse by nodes that have not observed the whole bus history). A Stop condition is signaled by SDA going high while SCL is high.

Besides the Start and Stop codition, there is another physical layer mechanism which is commonly used, and that is clock stretching. When a slave device needs a bit more time for processing, it can just assert the SCL line. So even when the master relases the SCL line, it remains low, and the master will detect this and wait. When the slave device is ready, it also releases the SCL line, so that it becomes high again, and the normal flow continous.

Data transport

Now that we descirbed the media access mechanism, we no longer need to consider the details of the SDA and SCL lines, and we can just consider data bits and start/stop conditions going over the bus. We can draw this as the diagram shown below: